Memory defect remedy analyzing method and memory test instrument

ABSTRACT

The invention relates to a hydraulic ratchet wrench with a double-action hydraulic cylinder piston drive with a gear pump ( 20 ) and a piston pump ( 21 ). According to the invention, a working stroke and a return stroke are controlled through a reversal of rotational direction of a pump motor ( 4 ), whereby the necessary flow volume is produced automatically via internal flow control valves, and without additional valve controls.

TECHNICAL FIELD

The present invention relates to a memory failure recovery analysismethod for application to a memory testing apparatus equipped with afailure recovery function which tests a semiconductor memory providedwith a failure recovery cell array, then decides whether a failing cellis recoverable, and if so, recovers it, and the invention also pertainsto a semiconductor memory testing apparatus using the failure recoveryanalysis method.

BACKGROUND ART

Semiconductor memory testers are roughly divided into a memory testingapparatus of the type testing semiconductor memories in wafer form priorto packaging and a memory testing apparatus of the type testingsemiconductor memories in packaged form. The memory testing apparatus ofthe type that tests semiconductor memories (hereinafter referred tosimply as memories) prior to packaging greatly differs from the memorytesting apparatus of the type testing packaged memories in thepossession of the function that decides whether a failing cell isrecoverable and, if so, recovers the failing cell.

In FIG. 1 there is depicted the general outline of the functionalconfiguration of a memory testing apparatus equipped with the failurerecovery function. The memory testing apparatus, denoted generally by100, comprises: a main controller 111, a pattern generator 112; a timinggenerator 113; a waveform formatter 114; a logic comparator 115; a groupof drivers 116; a group of analog comparators 117; a failure analysismemory 118; a failure recovery analysis processing unit 119; alogical-amplitude reference voltage source 121; a comparison referencevoltage source 122; and a device power supply 123. The main controller111, the pattern generator 112, the timing generator 113, the waveformformatter 114, the logic comparator 115 and the failure analysis memory118 are connected to a tester bus 124.

The main controller 111 is usually constituted by a computer, whichexecutes a user's prepared test program to control mainly the patterngenerator 112 and the timing generator 113, by which test pattern data,that is, address data, a control signal and expected value data, isgenerated by the pattern generator 112, then the test pattern dataexcept the expected value data is converted by the waveform formatter114 to a test pattern signal having a real waveform, and the testpattern signal is voltage amplified by the driver 116 to a signal of awaveform having an amplitude set in the logical- amplitude referencevoltage source 121, thereafter being applied to a memory under test 200formed on a semiconductor wafer WH to store therein the test data,

A response signal read out of the memory under test 200 is applied tothe analog comparator 117 which compares it with a reference voltageprovided from the comparison reference voltage source 122 to decidewhether it has a predetermined logical level (H-logic voltage, L-logiclevel), and the signal decided to have the predetermined logical levelis compared by the logic comparator 115 with the expected value data fedfrom the pattern generator 112; when a mismatch with the expected valuedata is found, it is decided that a memory cell of the address fromwhich the response signal was read out is failing, then fail data fromthe logic comparator 115 is stored in the address position of thefailure analysis memory 118 corresponding to that readout address, andat the conclusion of the test it is decided by the failure recoveryanalysis processing unit 119 whether the failing cell is recoverable ornot. In FIG. 1 there is shown the case where the write data and the readdata of the memory 200 are both one-bit, but when these pieces of dataare composed of plural bits, the numbers of drivers 116 and analogcomparators 117 used are the same as the number of bits.

With reference to FIG. 2 conceptually showing the redundant memory 200,a brief description will be given below of its internal configuration inwhich the number N of data bits is plural and spare lines are providedaccordingly.

In memory cell array groups which are so-called memory planes 201-0,201-1, 201-2, - - - , 201-N-1 are respectively stored zeroth bit databit-0, first bit data bit-1, . . . , N-th bit data bit-N of N-bit data.In the respective memory cell array groups (memory planes) 201-0, 201-1,201-2, - - - there are formed a plurality of memory arrays 202, and aspare cell line 203 is formed adjacent the position where the respectivememory cell arrays each are formed. The spare cell line is commonlycalled a spare line, which is formed by an arrangement of memory cellsof the same number as that of the memory cells on each address line inthe memory cell array 202; for example, two or more memory cells areformed in each of a column address direction COL and a row addressdirection ROW.

The failure analysis memory 118 comprises, as depicted in FIG. 3: astorage part AFM; a multiplexer MUX which selectively applies an addresssignal to an address terminal An of the storage part AFM; and an addressconverter ACN which converts an address signal in the test pattern datafed from the pattern generator 112 (see FIG. 1) to an address signal ofthe corresponding address signal of the failure analysis memory 118;upon each detection of a mismatch in the logic comparator 115, a writesignal WRITE is applied to a write control terminal WE of the storagepart AFM in synchronization with the corresponding fail detectionsignal. Fail data, which is the output from the logic comparator 115, isprovided to a data terminal Dn of the storage part AFM.

The addresses of the memory under test 200 have a one-to-onecorrespondence to the addresses of the storage AFM; if exactlyidentical, the address signal applied to the address converter ACNpasses therethrough intact.

The failure recovery analysis processing unit 119 comprises, as shown inFIG. 4, a control part 10 and a recovery analysis unit 20 which iscontrolled by the control part 10 to operate. The recovery analysis unit20 comprises a bit designating part 21, a latch circuit 22, processingpart 23, and an address generator 24.

During testing the memory 200, in the failure analysis memory 118 themultiplexer MUX selects the address signal fed to its input terminal Bfrom the address converter ACN and provides it to the address inputterminal An of the storage part AFM, and upon each occurrence of amismatch in the logic comparator 115, fail data from the logiccomparator 115 is stored in that address of the storage part AFMcorresponding to the address of the memory under test 200 for which themismatch is detected. Incidentally, each cell of the storage part AFM ispre-initialized to the “0” logic.

The fail data mentioned herein is data which has a bit of the “1” logicfor which a mismatch was found in the result of comparison between thedata read out of the memory under test 200 and the expected value dataand a bit of the “0” logic for which no such a mismatch was detected.

During the failure recovery analysis the multiplexer MUX selects addresssignals applied to its input terminal An from the address generator 24(FIG. 4) in the failure recovery analysis processing unit 119 andprovides the selected address signals to the address terminal An of thestorage part AFM, and the pieces of fail data are read out of thestorage part AFM one after another.

The N-bit fail data thus read out of the storage part AFM is provided tothe bit designating part 21 (FIG. 4) in the failure recovery analysisprocessing unit 119. In the bit designating part 21, data of the bit inthe fail data designated by the output from a bit designating register21A is fed via an OR circuit 21C to the latch circuit 22. That is,logarithmic value data of a counter 10F in the control part 10 isprovided to the bit designating register 21A, then the bit designatingregister 21A decodes the count value data, and the output from the bitdesignating register 21A enables any one of gates 21B-0, . . . , 21B-N-1provided corresponding to respective bits in the N-bit fail data,through which the corresponding bit in the fail data is provided to thelatch circuit 22.

The one-bit data thus provided to the latch circuit 22 is recognized bythe address signal from the address generator 24 as to form whichaddress was read out the fail data to which the one-bit data belongs,and furthermore, which bit in the fail data read out of that address isfailing, that is, the position on the cell line (called an address line)designated by an address on the memory cell array, is specified by thecontent (bit designating data) of the bit designating register 21A. Theprocessing part 23: reads thereinto, upon each latching of a “1” intothe latch circuit 22, the corresponding address and bit designatingdata; specifies the address and bit position of the fail data; countsthe number of failing cells at the specified bit position (memory plane)for each address line; upon conclusion of the readout from alladdresses, analyzes whether the address line is recoverable with thespare line 203 formed adjacent each memory cell array; and, ifrecoverable, the address line concerned is electrically replaced withthe corresponding spare line. Next, the counter 10F is incremented byone, then fail data of all addresses in the storage part AFM is read outtherefrom, then for the next bit number (on the next memory plane) ofthe fail data, the number of failing cells for each address line iscounted, and the address line, if recoverable, is replaced with thecorresponding spare line 203. Thereafter, the same recovery analysisprocessing as mentioned above is performed for each bit number of thefail data. In this way, a defective memory can be changed to anon-defective memory.

As described above, in the prior art the fail data of the bit designatedby the bit designating part 21 is sent to the processing part 23 bit bybit in address order. That is, the recovery analysis processing, inwhich the memory cell array groups 201-0, 201-1, 201-2, . . . shown inFIG. 2 are designated by the bit designating register 21A on agroup-wise basis and all the addresses of each memory cell array groupare read out, is carried out for each of the memory array cell groups201-0, 201-1, 201-2, . . . Accordingly, the prior art method isdefective in that much time is required for the recovery analysis.

An object of the present invention is to provide a memory recoveryanalysis method that enables a recovery analysis to be made in a shortertime than in the prior art, and a memory testing apparatus using therecovery method.

SUMMARY OF THE INVENTION

According to the method of the present invention, plural bits of faildata are ORed which are read out of a failure memory, in which the faildata is stored for each bit, and based on the result of ORing, theplural bits are simultaneously subjected to the recovery analysis.

The apparatus of the present invention is provided with: a failureanalysis memory for storing fail data which is the result of bit-wiselogic comparison of data read out of a memory under test and expectedvalue data; an analysis data bit designating part for outputting bitdesignating data for designating plural bits in the fail data read outof the failure analysis memory; a logic circuit supplied with the bitdesignating data from the analysis data bit designating part and thefail data, for outputting the OR of the designated bits in the faildata; and a processing part supplied with the output from the logiccircuit and the address from which the fail data was read out, forperforming a remedy analysis.

According to the recovery analysis method of the present invention, byORing plural bits of the fail data read out of the failure analysismemory, the data of the plural bits is compressed into single bit formand is subjected to the remedy analysis—this permits simultaneousrecovery of plural data bits and hence reduces the time for recoveryanalysis. When the data compressed into single bit form indicates afailure, the bit corresponding to the failing cell can easily be locatedby reading out the corresponding plural bits from the failure analysismemory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for explaining the general outline of thememory testing apparatus.

FIG. 2 is a diagram conceptually showing the internal configuration of aplural-bit-data memory under test which is provided with spare lines.

FIG. 3 is a block diagram for explaining the functional configuration ofa conventional failure analysis memory.

FIG. 4 is a block diagram for explaining the functional configuration ofa conventional failure recovery analysis processing unit.

FIG. 5 is a block diagram showing the principal part of an embodiment ofa memory testing apparatus embodying the failure recovery analysismethod according to the present invention.

FIGS. 6A, 6B and 6C are diagrams respectively showing examples of storedcontents of an analysis data bit designating memory 21D in FIG. 5.

FIG. 7 is a flowchart showing the procedure of an embodiment of thisinvention method.

FIG. 8 is a flowchart sowing an example of the procedure forone-bit-designating recovery analysis which is performed when impossibleby a plural-bit-designating failure recovery analysis.

FIG. 9 is a diagram depicting an example of bit designating data whichis output from a bit designating register 21A in the procedure shown inFIG. 8.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 5 illustrates an embodiment of the principal part of a memorytesting apparatus embodying the recovery analysis method according tothe present invention. The part depicted in FIG. 5 is the bitdesignating part 21 and has, as in FIG. 4, a bit designating register21A, and a logic circuit 21F comprising gates 21B-0, . . . , 21B-N-1each of which extracts a designated bit from fail data by bitdesignating data from the bit designating register 21A, and an OR gate21C for ORing the outputs from these gates.

In this embodiment the bit designating part 21 is further provided withan analysis data bit designating part 21D and a selector 21E forselectively outputting bit designating data from the analysis data bitdesignating part 21D and bit designating data from the bit designatingregister 21A. The analysis data bit designating part 21D is capable ofgenerating bit designating data for designating plural bits in faildata, and in this embodiment it is an analysis data bit designatingmemory.

Count value data of the counter 10F of the controller 10 is alsoprovided as an address signal to the address terminal Am of the analysisdata bit designating memory 21D.

In the analysis data bit designating memory 21D there is stored at leastone of pieces of bit designating data which enable plural ones of thegates 21B-0, . . . , 21B-N-1. This storage is set by a user's arbitrarywrite into the memory. FIG. 6A shows an example. This example shows thecase where the number of bits of the fail data is 16 and bit designatingdata is stored in addresses 0 to 3 for performing a remedy analysis ofthe fail data by steps of fours bits at one time. That is, in theanalysis data bit designating memory 21D having all cells initialized tothe “0” logic, the “1” logic is written in each of the cells of theaddress 0 which correspond to bits NO. 0, 1, 2 and 3 of the fail data;the “1” logic is written in the cells of the address 1 which correspondto bits NO. 4, 5, 6 and 7 of the fail data; and thereafter, the “1”logic is similarly written in each of the cells of the addresses 2 and 3which correspond to bits NO. 8, 9, 10, 11 and NO. 12, 13, 14, 15 of thefail data, respectively.

Referring to FIG. 7, a description will be given of an example of theprocedure for performing a failure analysis by use of such an analysisdata bit designating memory 21D. The selector 21E is assumed to becontrolled by the main controller 111 (FIG. 1) to select the bitdesignating data read out of the analysis data bit designating memory21D.

In step S1 the counter 10F is initialized, and in step S2 the analysisdata bit designating memory 21D is read out using count value data ofthe counter 10F as an address. Accordingly, bit designating data 111100. . . 0 in the address 0 of the memory 21D, shown in FIG. 6A, is readout, and the respective pieces of bit data are provided to the gates21B-0, . . . , 21B-15 of the logic circuit 21F, enabling the gates21B-0, 21-B-1, 21B-2 and 21B-3.

In step S3 the address generator 24 (FIG. 4) of the failure analysismemory is initialized. In step S4 the storage part AFM is read outaddressing by an address signal from the address generator 24.Incidentally, the multiplexer MUX in FIG. 3 is pre-controlled by themain controller 111 (FIG. 1) to select an address signal from thefailure remedy analysis processing unit 119.

In step S5 designated bits in the fail data read out of the storage partAFM are ORed. That is, in FIG. 5 respective pieces of data of 0-th to15th bits of the read-out fail data are provided to the gates 21B-0 to21B-15; in this example, since only the gates 21B-0 to 21B-3 are heldenabled, only those 0-th to 3rd bits in the fail data designated by thebit designating data are fed to the OR gate 21C, wherein they are ORed.

In step S6 a check is made o see if the OR calculated in step S5 is the“1” logic or not, and if it is the “1” logic, then in step S7 the numberof failing cells for the address line corresponding to the addresssignal from the address generator 24 (FIG. 4) is incremented by a 1.That is, if any one of the NO. 0 to NO. 3 bits of the read-out fail datais the “1” logic, the failing cell count value of the address lineconcerned is incremented by a 1. This processing is performed by theprocessing unit 23 (FIG. 4). In the case of designating a cell by theROW address and the COL address as depicted in FIG. 2, the number offailing cells is incremented by a 1 for these address lines.

In step S8 a check is made to see if all the pieces of fail data in thestorage part AFM have been read out, and if not, then in step S9 theaddress signal which is generated by the address generator 24 is steppedone stage, followed by a return to step S4. If it is decided in step S6that the OR is not the “1” logic, then the procedure goes to step S8.

Upon completion of reading out all the pieces of fail data in this way,a remedy analysis is performed in step S10. The number of failing cellsin each address line is analyzed, and a remediable address line isswitched to the corresponding spare line for all the bits NO. 0 to NO. 3at the same time. Accordingly, for example, even if only the bit NO. 1is failing in a certain address line, the bits NO. 0, NO. 2 and NO. 3are also switched to the spare line. This recovery analysis needs onlyto be made by the processing part 23 (FIG. 4) in the same manner as inthe prior art. The scheme used differs from the conventional one only inthat an address line is switched to a spare line for all of thedesignated plural bits at the same time.

Next, in step S11 a check is made to see if desired bits in the faildata have all been designated, and if not, then the counter 10F isstepped one stage in step S12, followed by a return to step S2.Accordingly, in this example bit designating data 000111100 . . . 0stored in its address 2 is read out from the analysis data bitdesignating memory 21D, and this data is provided to the gates 21B-0 to21B-15, by which only the gates 21B-4 to 21B-7 are enabled. In thisstate, all the pieces of fail data are read out in the same manner asdescribed above, then the pieces of data of the designated bits NO. 4 toNO. 7 are ORed, and based on the results of ORing, address lines for thebits NO. 4 to NO. 7 are simultaneously subjected to the recoveryanalysis processing.

Thereafter, similar processing is carried out, and when desired bits inthe fail data are all designated, that is, in this example, when therecovery analysis is completed by reading out the bit designating datafrom the address 3 of the analysis data bit designating memory 21D, theentire processing is concluded.

Conventionally, since the recovery analysis processing is performed foreach bit of the fail data, the readout of all pieces of fail data fromthe storage part AFM needs to be repeated by the number N of bits offail data, that is, 16 times in the FIG. 6A example, but this embodimentrequires only four repetitions; furthermore, the prior art requires 16repetitions of the analysis processing for address-to-spare lineswitching based on the failing cell count value for each address line,but this embodiment requires only four repetitions, and hence permitsreduction of the time for failure analysis.

The recovery processing of step S10 in FIG. 7 may also be performedafter completion of all bit designations as indicated by the brokenlines in FIG. 7. The bit designation of the fail data is not limitedspecifically to groups of four bits; the number of bits may differ foreach designation. Provision may be made to designate, for instance, sixbits NO. 0 to NO. 5, six bits NO. 6 to NO. 11, and four bits NO. 12 toNO. 15 as shown in FIG. 6B. Moreover, the bit designation need notalways be limited to consecutive bit numbers but only one bit may bedesignated. That is, for example, plural bit numbers which areempirically known to be almost free from the occurrence of failing cellsare designated together as many as possible, and only one bit for whichit is known that failing cells occur relatively easily is designated.For example, it is possible to sequentially generate such bitdesignating data as shown in FIG. 6C. In some cases, no bits need to bedesignated for one or more particular bit numbers; that is, it is alsopossible that some pieces of bit designating data do not designate anybits in the fail data. Additionally, all the bits of the fail data maybe designated at one time.

It is also possible to utilize a configuration which does not involvereading out the bit designating data from the memory 21D and in which:for example, the “1” logic is preset in each of plural stages of a shiftregister having stages of the same number as the bit widths of the faildata; the output from respective stages of the shift register are usedto form the bit designating data; and, upon each reading out alladdresses of the storage part AFM, the shift register is shifted stagescorresponding to the “1” logic. Alternatively, the bit designating datamay be produced by calculation upon each completion of readout of allfail data, that is, in step S2 in FIG. 7. To this end, the analysis databit designating memory 21D in FIG. 5 is used as an analysis data bitdesignating part for generating bit designating data, and when itbecomes necessary to generate the bit designating data, the control part10 instructs the analysis data bit designating part to conduct thecalculation; if necessary, parameters necessary for the calculation areprovided to the analysis data bit designating part. As will be seen fromthe above, the bit designating data may also be generated by software.

In the embodiment of FIG. 5, the same failure analysis processing as inthe prior art could be performed by selecting the bit designating datafrom the bit designating register 21A by the selector 21E and applyingit to the logic circuit 21F. Further, by setting desired data in thecounter 10F or bit designating register 21A with the selector 21E heldin the state in which to select the bit designating data from the bitdesignating register 21A, a check can be made to determine which one ofplural pieces of, for example, compressed bit data is a true failingcell. For example, in the case of using the bit designating datadepicted in FIG. 6A, the 4-bit data produced by the bits NO. 4 to NO. 7of the fail data is compressed into 1-bit data and the recovery analysisprocessing is performed; even if it is decided that recovery isimpossible, there is the possibility of obtaining a recovery solution bycarrying out the recovery analysis processing for each bit number of thebits NO. 4 to NO. 7 of the fail data. That is, for example, when “1”logic data indicating a failure is present in different addresses of thebits NO. 4 to NO. 7 of the fail data, if the recovery analysisprocessing is performed after compression of the bits NO. 4 to NO. 7 ofthe fail data, recovery is needed for four address lines. If, however,respective bit numbers of the bits NO. 4 to NO. 7 of the fail data aredesignated and the recovery analysis processing is carried out for eachbit number, one piece of the “1” logic data indicating a failure isprovided for each bit number; hence, it is necessary only to performrecovery for each address line.

Such a procedure is carried out, for example, as follows: Uponcompletion of the readout of all data in step S8 in FIG. 7, a check ismade in step S21 in FIG. 8 to see if the failing cell recovery ispossible; if impossible, the output from the bit designating register21A is selected by the selector 21E (FIG. 5) in step S22; the bitdesignating bit, which designates one bit of the portion concerned, thatis, one of the bits NO. 4 to NO. 7 of the fail data, the bit NO. 4 inthis example, is provided from the bit designating register 21A to thelogic circuit 21F since the count value 4 of the counter 10F is providedto the bit designating register 21A; in step S23 all addresses of thefail data storage part are read out; in step S24 the recovery analysisprocessing is carried out for the output from the logic circuit 21Fprovided for the read-out data; in step S25 it is decided whether therecovery analysis processing for the designated one bit of the portionconcerned has been completed; and, if not, the counter 10F is steppedone stage in step S26 and the procedure goes to step S22, in whichfailure analysis processing is performed designating the next bit NO. 5alone. In this way, the pieces of bit designating data, each designatingone of the bits NO. 4 to NO. 7 as shown in the thick-lined frame, aresequentially output from the bit designating register 21A, and thefailure recovery analysis processing is carried out on a bit-wise basis.

Upon completion of the failure recovery analysis processing for thedesignated one bit of the portion concerned, that is, upon completion ofthe failure recovery analysis processing for the bit NO. 7 in thisexample, the content of the counter 10F, which is the numerical dataprior to the 1-bit designated failure recovery analysis processing, ispreset to data of numerical value 4 in this example, then the selector21E is switched to the selection of the output from the bit designatingmemory 21D, after which the procedure goes to step S11 in FIG. 7.Incidentally, when the 1-bit designated failure recovery analysisprocessing is begun in step S22, the count value 4 of the counter 10F atthat time is stored in a register in the control part 10, and the storedvalue is used to restore the counter 10F in step S27. When it is decidedin step S21 that recovery is possible, the recovery processing isperformed, after which the procedure goes to step S11 in FIG. 7.

In FIG. 5 it is also possible to omit the bit designating register 21Aand the selector 21E and to provide the bit designating data from theanalysis data bit designating part 21D directly to the logic circuit21F. The bit width of the fail data, that is, the bit width of the datathat is stored in the memory under test 200 is not limited specificallyto 16 bits.

As described above, according to the present invention, all data bits ofthe fail data, which are output from the logic comparator 115 duringtest, are stored intact in the failure analysis memory 118, and at thetime of the recovery analysis processing arbitrary plural bits in thefail data are compressed for recovery analysis processing, so that thetime for recovery analysis processing can be reduced accordingly.Furthermore, when recovery is impossible with compressed fail data, thefail data is read out of the failure analysis memory 118 for eachoriginal bit NO. of the compressed fail data, and the analysisprocessing is performed bit by bit.

1. A memory failure recovery analysis method that comprises: rending outplural bits of fail data from a failure analysis memory having storedtherein the fail data for each bit of an addressible location in amemory under test; ORing two or more but less than all of the pluralbits of the fail data read out of the failure analysis memory;performing recovery analysis processing based on the ORed result; andproviding memory failure recovery analysis for all of the plural bits ofsaid fail data by one or more repetitions of ORing and performing therecovery analysis processing for other bits in the plural bits notprocessed; wherein the recovery analysis processing is performed bit bybit when the recovery analysis processing based on the result of ORingof the plural bits is decided impossible.
 2. The memory failure recoveryanalysis method as recited in claim 1, wherein the two or more but lessthan all of the plural bits are selected according to failure statisticsof the memory under test.
 3. A memory testing apparatus comprising: afailure analysis memory that stores plural bits of fail data resultingfrom a bit-wise logical comparison between data read out of a memoryunder test and expected value data; an analysis data bit designatingpart that outputs bit designating data, which designates two or more butless than all of the plural bits in the fail data read out of thefailure analysis memory; a bit designating register that outputs bitdesignating data for designating one bit in the fail data; a selectorfor selecting one of the output bit designating data from the bitdesignating register and the output designating data from the analysisdata bit designating part; a logic circuit supplied with the bitdesignating data selected by the selector and said fail data thatoutputs the OR of designated plural bits in the fail data; andprocessing part supplied with the output from said logic circuit and anaddress by which said fail data was read out that performs recoveryanalysis processing for the memory under test.
 4. The memory testingapparatus as recited in claim 3, wherein said analysis data bitdesignating part is formed by a memory which has the same bit width assaid fail data, designates different bit numbers in the fail data, andstores plural pieces of bit designating data at least one of whichdesignates plural bit numbers, and from which that one piece of bitdesignating data is read out and provided to said logic circuit.
 5. Thememory testing apparatus as recited in claim 4, wherein said pluralpieces of bit designating data are produced so that all bits of the faildata are designated by these pieces of bit designating data.
 6. Thememory testing apparatus as recited in any one of claims 3 to 5,wherein: said analysis data bit designating part is said memory; saidbit designating register is a decoder for outputting bit designatingdata for designating one bit in response to the input data; and acounter is provided which supplies count data as an address to saidanalysis data bit designating part and to said bit designating register.7. A memory failure recovery analysis method which reads out fail datafrom a failure analysis memory having stored therein the fail data foreach bit and performs failure recovery analysis processing, the methodcomprising: ORing plural bits of the fail data read out of the failureanalysis memory; performing recovery analysis processing based on theORed result; and if the recovery analysis processing based on the ORedresult indicates recovery is not possible, performing the recoveryanalysis processing bit by bit for each of the plurality bits indicatinga fail.
 8. The memory failure recovery analysis method as recited inclaim 7 that comprises: performing at least once the recovery analysisprocessing based on the result of ORing of the plural bits of the faildata; and performing the recovery analysis processing for all bits ofsaid fail data by at least one or more repetitions of the recoveryanalysis processing.
 9. The memory failure recovery analysis method asrecited in claim 7 or 8 that comprises: reading out fail data from thefailure analysis memory at arbitrarily designated addresses; anddesignating an arbitrary bit in the read-out fail data and decidingwhether the designated bit is fail data.